1. Field of the Invention
This invention relates generally to semiconductor devices using bulk semiconductor for achievement of highly miniaturized transistors with enhanced performance. The invention also relates to a method of fabricating the same.
2. Description of Related Art
Today, metal insulator semiconductor field effect transistors (MISFETs) using silicon-on-insulator (SOI) substrates with a fully depleted channel region are under diligent research and development at some leading companies and laboratories, for use as transistors suitable for microfabrication and performance enhancement schemes. The MOSFETs of this type will be referred to as fully depleted SOIFETs or simply FD-SOIFETs. Typically these FD-SOIFETs are designed to have a specific thickness and impurity concentration low enough to permit a silicon layer overlying an oxide film for use as a channel region to be fully depleted.
In such FD-SOIFETs, a vertical electric field from a gate electrode is partly allotted by a buried oxide film at the bottom of a channel region, resulting in a likewise decrease in vertical electric field being applied to the channel region. As a result of such decrease or “relaxation” of this channel region's vertical electric field, the channel region increases in carrier mobility, leading to an advantage or merit as to the obtainability of higher current driving ability or “drivability.”
Unfortunately in view of the quest for higher integration and miniaturization, the advantage of FD-SOIFETs does not come without accompanying several penalties. Examples of the penalties are as follows. First, in order to suppress the so-called “short channel” effect, it becomes inevitable to employ SOI substrates with ultra-thin silicon layers. Second, the use of such ultrathin silicon layers would result in an unwanted increase in parasitic resistance values. Third, as a channel region surrounded by oxide films which are ordinarily less in thermal conductivity than silicon, the conductivity of heat generated in self-heatup regions near a drain is made inferior, resulting in an increase in degradation of performance. Another penalty is a problem that the SOI substrates are relatively less in quality whereas gate dielectric films stay less in reliability, causing possible plasma damages to increase accordingly. A further penalty lies in high price of the SOI substrates at least at the present time.
In contrast, attempts are made to avoid the above-noted problems or demerits of FD-SOIFETs by employment of bulk semiconductors while letting them offer similar effects to the FD-SOIFETs. An example of this approach proposed today is to realize a pseudo-SOIFET by use of a “p/n−/p” multilayer structure including a p-type channel region and its underlying lightly-doped n (n−) type layer depleted due to a built-in potential. Examples of the p/n−/p structure are found in several documents—for example, 1) T. Mizuno et al., 1991 Symp. on VLSI Tech. at page 109 (1991), 2) M. Miyamoto et al., IEDM Tech. Digest, p. 411 (1998), and 3) Ishii and Miyamoto, Published Unexamined Japanese Patent Application No. 7-335837.
The proposed pseudo-SOIFET structures are still encountered with many problems to be solved, one of which is the difficulty in obtaining any sufficient performance on the order of submicrons of minimum feature size. More specifically, the pseudo-SOIFETs as taught from the above-identified three documents (“D1-D3”) are arranged so that a channel region is greater in depth (thickness) than its associated source and drain diffusion layers. This is a serious bar to suppression of short-channel effects in the case of further miniaturization or shrinkage. Additionally if a semiconductor layer of such channel region is formed of an impurity-doped layer low in impurity concentration enough to realize a fully depleted element, then punch-through can disadvantageously take place in cases where the gate length (channel length) is shortened to be on the order of submicrons. And, in order to prevent this punch-through, complicated drain structures should be required, such as the ones as disclosed in the documents D2-D3.
It is also noted that with the structures as taught by D2-D3, the bottom portions of source/drain diffusion layers to be fabricated by counter-doping techniques are made deep enough to reach the p-type layer beneath the n−-type layer. This would result in an undesired increase in junction capacitance of the source/drain, thereby making difficult achievement of high-speed operabilities.
Further note that the documents D2-3 merely suggest the use of ion doping or implantation methods as the method of obtaining the p/n−/p structure of the channel region. Simple use of such ion implantation methods for obtaining the p/n−/p channel structure can reach a limit in further reduction of channel region impurity concentration and thickness.